DIGITAL SYSTEMS ENGINEERING DALLY PDF

adminComment(0)

Download full-text PDF. Digital Systems Engineering. William J. Dally and John W. Poulton. Errata as of September 26, Page Correction. 1 - INTRODUCTION TO DIGITAL SYSTEMS ENGINEERING. pp · https://doi. org//CBO Access. PDF; Export citation. Lectures: MW in Urbauer Textbook: Dally and Poulton, Digital Systems Engineering. Grading: Approximate weighting for grade determination.


Digital Systems Engineering Dally Pdf

Author:ANISSA EBBERS
Language:English, Indonesian, Portuguese
Country:Morocco
Genre:Biography
Pages:564
Published (Last):09.05.2016
ISBN:822-4-33602-454-1
ePub File Size:24.55 MB
PDF File Size:18.47 MB
Distribution:Free* [*Registration Required]
Downloads:45630
Uploaded by: TINY

Digital system engineering - Ebook download as PDF File .pdf), Text File .txt) Dally, William J. Digital systems engineering / William J. Dally, John W. Poulton. Köp Digital Systems Engineering av William J Dally, John W Poulton på Bokus. com. PDF-böcker lämpar sig inte för läsning på små skärmar, t ex mobiler. Skim Dally/Poulton “Digital Systems Engineering”. Chapter 3. Skim Overview Paper: raukhamatfrogal.cf; Includes running Stat Eye.

Dally, William J. Dally, John W. Electronic digital computers - Design and construction. Digital first principles. The book avoids the handbook approach of describing how things.

This course gives you a complete insight into the modern design of digital systems fundamentals from an eminently practical point of view. Quarta pagina. Dally, R. This chapter gives an in-depth treatment of major noise sources including power supply noise, signal return coupling, crosstalk, inter-symbol interference, and parameter offsets. Lower-level noise sources including alpha particles, thermal noise, shot noise, and flicker noise are briefly treated. The engineering models of these noise sources are then used to introduce the use of noise budgets, the concept of noise immunity, and the calculation of error rate based on statistical noise models.

This treatment of noise prepares the reader to understand the major problem in the design of signaling systems presented in Chapters 7 and 8. A signaling convention involves encoding information into a physical quantity typically current or voltage , providing a reference against which this quantity is measured, the design of transmitters to couple signal energy into the transmission medium and terminators to absorb energy and prevent unwanted reflections, and a method for controlling signal transitions to limit the spectrum of transmitted energy.

The signaling convention determines to a large extent the reliability, speed, and power consumption of a system. A good signaling convention isolates a signal from noise, providing noise immunity, rather than attempting to overpower the noise with noise margin.

Most signaling conventions in common use are quite poor, based on standards that are accidents of history rather than on careful design to isolate noise sources. For this reason, many modem systems define their own signaling conventions rather than employ these standards.

This chapter introduces the concepts of voltage-mode and current-mode transmission, unipolar and bipolar signaling, series and parallel termination, references, and differential signaling. Undertermination, rise-time control, pulsed signaling, and multi -level signaling are also described. We develop methods for calculating the signal magnitude required to transmit a signal reliably in the presence of noise and show that, with adequate noise isolation, very low voltage signal swings mV are sufficient.

Chapter 8 describes more advanced concepts including techniques for dealing with lossy RC and LRC transmission lines, simultaneous bidirectional signaling, and AC signaling. A digital system uses a timing convention, along with a signaling convention to govern when to place a new symbol on a signal line and when to sample the line to detect the symbol. A good timing convention is one that maximizes performance by reducing and compensating for sources of timing noise, skew and jitter.

It is the uncertainty in the timing of a signal, not the delay, that limits the rate at which a system can operate. Chapter 9 discusses the fundamentals of timing conventions. The methods used to encode timing on signals are described and the concepts of timing noise and timing budgets are introduced.

The chapter goes on to develop methods for minimizing skew and jitter using both open-loop and closed-loop timing. A discussion of clock distribution techniques closes the chapter. Closely related to timing is the problem of synchronization, determining the relative order of two events, which is discussed in Chapter Synchronization is required when sampling asynchronous inputs into a synchronous system, or when a signal traverses the boundary between two clock domains.

Digital Systems Engineering

When a signal is synchronized there is some probability that the synchronizer will be driven into a metastable state, unable to resolve which event came first, and stay in that state long enough to cause a synchronization failure.

This chapter introduces the problem of synchronization, describes metastability, synchronization failure, and gives methods to calculate the probability of synchronization failure. A section on synchronizer design recognizes several special cases of synchronization and describes how to build fast synchronizers that exploit these special cases to XXIV PREFACE avoid the normal synchronizer delays. Finally, the chapter describes methods for asynchronous design that avoid the problem of synchronization.

Circuits for signaling and timing are described in Chapters 11 and 12 respectively. Chapter 11 presents working circuits for the transmitters, receivers, and terminations needed to build the signaling systems described in Chapters 7 and 8. Particular attention is paid to techniques for managing noise and compensating for process, voltage, and temperature variations.

A pair of current mirrors is used to generate the bias voltages. Similar methods can be 6 With unipolar differential signaling. No reference is required. In this case the two logic levels are denoted by equal amounts of current flowing in opposite directions. Waveforms for the rise-time-controlled driver are shown at the right side ofthe figure.. To avoid this. Like Goldilocks's porridge. On the other hand. The driver is divided into four current-mode drivers.

Depending on the degree of accuracy needed in the rise time. As a result.. If the current drivers turned on instantaneously. The segments of the driver are sequenced on by the taps of a delay line so that each segment turns on 0. Too fast a rise time couples energy into parasitic tank circuits Section 6. Because of the gain of the output stage. Because the rise time of a typical CMOS gate can vary by 2: The RC output of the predriver gives a long predriver rise time.

Until the slowly rising predriver output reaches the threshold voltage of the output stage.

Editorial Reviews

The figure shows an ideal predriver with an RC output circuit driving a switched current-source output driver. Waveforms of the circuit are shown at the right side of the figure.

The situation is illustrated in Figure Consider the abstract voltage-mode driver circuit shown in Figure Because of the delay. Once the predriver voltage reaches the output threshold. This results in a relatively fast output rise time. To get a tr of half a bit cell.

RC rise-time control is not a viable technique for rise times that are greater than about one-tenth of the bit cell. This results in a long output delay.

On a falling output. When the driver switches from high to low. The pull-up and pull-down drivers are segmented into four smaller drivers with equal output impedance. Suppose there are n stages. When the input switches from low to high. Table shows the values of conductance and resistance for a four-stage voltage-mode driver with a [2 termination. Only three stages are shown because the fourth stage.

Each driver is illustrated here as a pair of resistors selectively connected to the output by a switch. A reference signal. As shown in the waveforms at the right side of the figure. To reject noise primarily due to IR supply variations. When the line is not discharged. Figure shows the latter approach. At each intermediate point during the switching process the connected resistors form a voltage divider so that the switching linearly ramps the open-circuit output voltage between the two supplies..

To see that the ramp is linear. The voltage swing on the line is set by the width of the discharge pulse. Adaptations of the drivers described above for terminated transmission lines can achieve both of these functions.

Care is required in routing the reference signal to keep its capacitance balanced with that of the line and to make most noise couple equally into the line and the reference so it can be canceled. This pulse is usually generated by a circuit that tracks the characteristics of the driver and the line so that the voltage swing remains constant across process. The driver gives a linear ramp on in current and the ramp off is usually controlled by the driver devices dropping out of saturation as the voltage approaches the supply.

Its output impedance damps the tank circuit. This gives the circuit a break-before-make action that eliminates overlap current. The transmitter multiplexes a four-bit input. It is useful to think of the earlier of these two clocks as the on-clock because it turns the current source on and the later clock as the off-clock because it turns the current source off.

Each input is tied to one gate of a stack of three NFETs that form a clocked current source tied to the line. The other two gates are tied to two clocks. A simple multiplexing transmitter is illustrated in Figure The current source drives the line only when both clocks are high. A transmitter with gain less than 1 can have bandwidth greater than the gain-bandwidth product of the technology by multiplexing several output signals together in the transmitter under control of a multiphase clock.

When operated as bipolar. Stated differently. In some cases feedback from the line or reference is used to terminate the pulse once the line has been discharged to the desired voltage. When driving LC loads. This circuit is the parallel combination of two stacks with the transistor positions reversed between the two stacks. Better performance and reduced area can be achieved by qualifying the off-clock with the data and driving a stack of two FETs with the on-clock and this qualified off-clock as illustrated in Figure The circuit of Figure uses a stack of three FETs to combine the two clocks with the data signal.

The result is that the two input clocks see the same effective threshold and thus switch without relative phase shift. The off clock. Because the on-clock and off-clock drive transistors at different positions in the stack.

The figure shows one multiplexer input. This effect can be eliminated by replacing the clocked part of each stack in Figure with a two-input symmetric gate. The circuit of Figure introduces timing offsets because the transistors at different positions in the stack have different threshold voltages due to the body effect and thus switch at different points in time. The multiplexer must be fast enough for its output.

The input multiplexer accepts full-swing inputs dO: The circuit of Figure consists of three stages: A multiplexed transmitter can also be implemented by multiplexing before the predriver and output stage. Each input of the multiplexer consists of a series pair of NFET pass gates controlled by an on-clock and an off-clock. This arrangement requires less circuitry and puts a smaller capacitive load on the output than the output-multiplexed circuit of Figure Voo eliminates dead time in the operation of the output stage.

The figure shows a prototypical data eye Chapter 6 in [LeeMess94] representing the physical quantity encoding one binary symbol. Systematic jitter occurs when the duration of the output bits is uneven in a repeatable manner. This systematic error can be a factor in an overall timing budget. The resolution and offset in these two dimensions determine the size of the eyeopening required for reliable detection of the signal. Shortly after the predriver starts switching.

The light shaded rectangle indicates the size of the gross timing margin width and the gross voltage margin height. In the voltage dimension. For proper operation. In the time dimension. In this section we will be concerned with receivers that detect voltage. A multiplexing transmitter may exhibit systematic jitter if the phases of the multi phase clock used to control the multiplexer are not evenly distributed or if delays between the clock signals and the output are not carefully matched.

A receiver should have good resolution and low offset in both the voltage and time dimensions. The dark-shaded rectangle represents the aperture time width and sensitivity height of the receiver.

Dally 98 w dally and j poulton digital systems

The second advantage is reduced timing uncertainty. For these reasons. A regenerative clocked amplifier can amplify the smallest signals up to full swing.

There are four main advantages to combining the functions of detection and sampling into a single circuit. The separate design adds two elements to the timing budget: A bank of clocked amplifiers operating as a demultiplexing receiver Section Only if the dark rectangle remains entirely within the light rectangle. For completeness.

As shown in Figure b. Only during the aperture time of the flip-flop is the detected value. Figure a shows the two tasks separated.

A static amplifier. With the single-clocked amplifier. The signal x is then sampled by an edge-triggered flip-flop with a clock. By choosing one or both offsets to be negative.

With the functions separated. A reference inverter. This technique in effect turns the inverter into a sequential differential amplifier with the primary source of offset becoming the variation in the reference over time. Inverters can also be used effectively by compensating for their variations. Combining the sensitivity with the offset. One approach is to use a switched capacitor circuit to measure and cancel the offset voltage of the inverter. A gain ofthis magnitude usually requires stages of amplification.

For a tight noise budget. This analysis should not imply that the inverter is without merit for use in a static receiver. More importantly. For some processes with lower DC gains. There are two ways inverters can be used effectively in receivers.

As long as the threshold voltage of the receiver inverter tracks the threshold voltage of the reference inverter. For this reason inverters are in widespread use as receivers on CMOS chips. Recall from Section 4. The input-referenced offset voltage of the inverter is reduced by the gain of the input stages and hence is less of a problem in this configuration.

Multiplying the inverter gain 20 by the gain of the earlier stages gives a high overall gain and hence a sensitive amplifier. Another approach to compensating for the variation in the threshold voltage of inverter receivers is illustrated in Figure In - IAI With an output swing of 2. If the current bias is too low. The offset voltage for these circuits depends primarily on the matching of two identical components e.

One approach to biasing a source-coupled amplifier is to use a replica-biased circuit. Static differential amplifiers can be built using either a source-coupled pair Section 4. Their primary advantage is a relatively low offset voltage compared with an inverter. An alternative approach is to use a self-biasing amplifier such as the Chappell amplifier [Chap88] shown in Figure The current-source bias must be set to balance output voltage swing against input common-mode range.

Static differential amplifiers also are largely insensitive to power supply variation in contrast to the inverter. Most source-coupled differential amplifiers have a limited common-mode operating range. At the same time. The proper bias depends on process variation. This circuit sets the bias voltage to give the desired output swing into a given load circuit.

An excessive bias. The input voltage must be high enough to bias the current source on and put the input transistors into the saturation region. The single-ended Chappell amplifier Figure a is a source-coupled Jut out in-. This results in negative feedback that drives the bias voltage to the proper operating point. A symmetric variation on the Chappell design that we have found useful is shown in Figure b. This circuit uses two current mirrors for the load.

The selection depends on the requirements for common-mode range and input isolation. The gate-isolated sense-amplifier of Figure c provides complete input isolation but at the cost of limiting the input common-mode range.

The complementary clocked sense-amplifier of Figure b has the advantage of a rail-to-rail common-mode range. Either of the clocked differential amplifiers described in Section 4. The negative feedback control of the bias current is the same as for the straight Chappel amplifier. The resulting amplifier has a large common-mode range. One approach to increasing the input dynamic range of a source-coupled amplifier is to combine an NFET source-coupled pair with a PFET source coupled-pair.

If the bias current is too low high. The single-ended Chappell amplifier is not suitable for driving subsequent stages of differential amplifiers. Figure shows how this is done in two steps: When the clock. This gives good rejection of timing noise and low-frequency compared with the data rate voltage noise.

We can describe the operation of the amplifier as sensing the convolution of the impulse response. Because this amplifier is integrating only half the time and precharging the other half. This has the advantage of rejecting highfrequency noise that will tend to average out over a bit cell but has the disadvantage of reducing immunity to low-frequency noise because the low-frequency noise is being integrated across times where the signal amplitude is reduced.

In the presence of high-frequency noise of significant amplitude. At the end of the integration period. The sense node lags the input because of the RC delay of the transmission gate. As shown in Figure c. This gives a reversed impulse response that exponentially falls off to the left with the RC time constant of the transmission gate.

These are all shown time reversed h -t so that they correspond to the weight applied to the input signal at a given point in time. It responds with equal weight to the input signal during the entire integration period.

It ramps up with the rise time of the clock to a peak value and then falls off exponentially with the time constant of the regenerative circuit as the sense nodes of the amplifier diverge. One method for shaping the current pulse is. Optimal filtering theory tells us that the ideal impulse response is that of a matched filter.

In the presence of timing noise. The ramp from the peak of the response to zero is set by the rise-fall times of the clocks controlling the transmission gates. A filter matched to the impulse response of the data has a timereversed impulse response that has a shape identical to that of the data eye.

When the clock rises. This response is almost exactly the reverse of the pass-gate input sense amplifier. Figure b shows the impulse response of a gate-isolated sense amplifier Figure c.

A complementary clocked sense amplifier Figure b has the impulse response shown in Figure a. For the first two waveforms. The response is zero until the clock rises.

As illustrated in Figure A clock with n equally spaced phases sequences an array of n sense amplifiers to take n equally spaced samples of an input signal each clock cycle. Here the gate voltage for the current-source transistor. In practice. With the appropriate choice of parameters. The current pulse is foreshortened. The higher rate is required on the receiver to recover timing information as well as data. The eight outputs of the receive amplifiers.

S Tracking receivers. With a multiplexing receiver. Oversampling clock receivers require at least three samples per bit cell. To stretch the period during which all eight signals are valid. Figure shows a 1: The waveforms show the situation where the even phases are used to sample cell edges for clock recovery and the odd phases are used to sample the data. Waveforms illustrating typical operation ofthis circuit are shown in Figure A single input signal. This stretches the valid period to five phases.

These receivers typically recover timing information by periodically shifting their sample points by a half bit cell to sample the timing and then shifting the sampling back to resume data sampling. An adjustable highvoltage power supply charges a capacitor to a preset voltage. A typical current waveform is shown in Figure c. A lumped circuit equivalent for an HBM tester.

This is particularly true in dry climates and air-conditioned environments in which a test-assembly technician can easily acquire a static body charge. Many Ie fabricators use an instrument that simulates this type of event. The circuits on a chip that are connected to the chip's external interface the bond pads for input.

The goal of electrostatic discharge ESD protection circuitry is to allow such an event to occur without damage to the chip's internals. These high-voltage stressing events almost always occur when a chip is being handled by a person or a robot during test.. The ESD protection circuitry in the chip clamps the voltage between any pair of pins to a few volts. A spark. Rise time is usually very fast compared with the event duration.

Other types of testers are. For a typical ESD test. As the technician's hand closely approaches a chip. Ensuring higher levels of ESD protection therefore inevitably compromises performance. FET gates can also be stressed in a secondary way by large fields between source and drain. Class I devices are allowed to fail at 2 kV. Class 2 devices fail between 2 and 3 kV. The result is a permanent shift in the device's threshold voltage and consequent degradation of performance. Tox is 70 X During normal chip operation these devices are never energized and simply represent low-pass filters between pad and internal circuitry.

Class 3 devices must withstand up to 4 kV. Because an ESD event can drive current into a chip between any pair of pins. A particularly unpleasant scenario is an ESD event that occurs when a chip is powered up. ESD protection circuitry uses large-area parasitic devices of various kinds attached to the bond pads and series impedances between pads and internal circuitry. In our example 0.

Although ESD damage often occurs during handling and assembly operations. The DoD standard defines various classes ofESD protection according to failure voltage threshold. Under these circumstances. After the series of stresses has been applied. The critical voltage for breakdown in Si02 is about 7 x VIM. As fabrication technology scales down. When the drain current reaches a critical value. Neither of these breakdown processes is necessarily fatal to the parasitic diode.

The interconnect wiring. This positive feedback process. This breakdown phenomenon is not necessarily destructive aside from the likelihood of hot-electron wear-out. During ESD events. The voltage. The multiplication of carriers is called avalanche breakdown and leads to rapidly increasing conduction.

A plot of breakdown drain current for an FET is shown in Figure If the junction is a FET source-drain terminal. The source and drain diffusion terminals of an FET form diodes with their associated substrate material.

Under reverse bias. I CRIT. This phenomenon leads to a third breakdown mechanism. At high reverse voltages. These diodes are normally lightly reverse biased and are considered parasitic elements during normal chip operation.

EE273 Lecture 1 Introduction to Digital Systems Engineering. Logistics

The hole-electron pairs that are generated themselves become carriers. Field-effect transistors can be thermally damaged by more complex mechanisms. Electrostatic discharge currents. Even in the absence of carriers with sufficient energy to ionize lattice atoms. The critical current feri! An ESD protection network is usually composed as shown in Figure and consists of four elements. Because ESD currents are quite large. It must handle very large currents. The primary shunt devices are the first line of defense against ESD damage.

The secondary shunt is referred to the local power supply of the protected elements to minimize the voltage across individual devices.

The power supply networks are the most robustly wired nodes in a chip. The secondary shunt further limits the voltage excursion presented to the protected circuitry. The current that flows through these shunts is usually quite small and is limited by the series element. The series impedance. Current from positive ESD events is carried by normal FET drain current for low-voltage events and by punchthrough for larger ones.

Such field devices are usually considered unwanted parasitics. During a positive-going ESD event. The ESD ground network carries the current between the two pads through the complementary devices in each pad. Note that this strategy works even if the ESD current flows into one signal pad and out another. The punchthrough phenomenon is enhanced by the presence of a gate terminal.

During negative-going ESD events. Both Voo and ground supply networks are co-opted to carry ESD currents away from these devices. The leading edge of the event forward biases the BE junction of the PNP protection device in the upper pad. By examining the cross section of the dual-diode arrangement. A typical arrangement of layers is shown in Figure b.

These bipolar devices are critical to the correct operation of the dual-diode primary shunt for signal-pad-to-signal-pad ESD events. The clamp voltage for these junction devices is essentially independent of other CMOS process variables. Because latchup during circuit operation is usually fatal to the chip. This device also called a silicon-controlled rectifier rSCR] or thyristor is usually undesirable.

A combination of.

During normal power-up. The inverter's input is an RC delay circuit with a time constant of 10 itS or so. With both devices on.

This shunt current encourages ESD currents to flow mainly in the BE junctions of the protection devices. To avoid depending on the purposely poor bipolar emitter-collector conduction to carry ESD currents. The shunt contains a very wide. A power supply shunt. Some IC manufacturers provide more exotic primary shunt devices. A very large resistance Ro discharges the capacitor during power-down. Heat generated in the resistor is not easily shed and could lead to failure of the device.

In older CMOS processes. If the protected node tries to swing below ground. Although diffusion resistors are possible. Usually the series resistor is of the order of a few hundred ohms.

A typical circuit is shown in Figure Some processes offer a "silicide blank" mask layer that allows the designer to remove the silicide on poly and diffusion in selected areas.

N-well resistors are a good option in processes in which the N-well resistance is well controlled and characterized. Input capacitance for a typical receiver is of the order of Older designs sometimes used polysilicon resistors. If the signal tries to swing above the local Voo voltage.

A better option is to place the resistor in the silicon substrate. Poly without silicide has resistance of a few tens of ohms per square. Poly is also completely surrounded by a thick field oxide whose thermal conductivity is low 1. This feature allows resistors to be built using poly.

Polysilicon resistors are not a particularly good idea in new designs. During an ESD event. If the burst of electrons produced during such an event gets collected on the N-well of a normal CMOS circuit within the chip. These measures include the addition of small-value resistors in series with the drain of each FET connected to a pad.

This can result in overheating nearby metal-to-silicon contacts. ESD primary shunts and the FETs in pad output drivers are spaced some distance away from chip internal circuitry. Special layout rules are usually required for FETs that drive pads. It is often advantageous to place the primary shunt devices out at the die perimeter.

As previously mentioned. These carriers can propagate for some distance. These and other measures tend to reduce the speed of output drivers. They may. Most fabricators require the addition of primary shunt diodes on outputs.

Future signaling system designs will not be able to take full advantage of device scaling because of these problems. In modem processes and especially for low-swing.

In some cases. In the case of a below-ground signal excursion. The extra distance between emitter and possible. Guard rings are always heavily contacted and robustly wired to the power supply networks in continuous metal. Ensuring uniform current distribution is especially important in FETs whose drains are connected to a pad. This section is intended merely as an introduction to a complex topic.

Care is required in the layout of conductors and via-contact arrays that carry these currents. The arrangement shown in Figure ll b should be avoided. The illustration shows a metal-to-silicon connection typical of an ESD protection diode.

Sources and drains for driver FETs should be contacted uniformly and as densely as possible along the full width of the device. Failure to do so could lead to current crowding in the FET channel.

The written guides for this part of the design process tend to be hard to obtain from vendors and difficult to understand. In Figure ll a. This arrangement leads to a uniform current distribution across the contacts in the horizontal direction. IC fabrication vendors differ substantially in their recommendations for the construction of effective ESD protection devices.

Current is delivered from one side of the contact array. These are very effective collectors of wandering minority carriers. In particular. Some of these considerations are outlined in Figure A single. Three termination schemes transmitter-only or self-source-terminated.

An automatically adjusted bias control sets the signal current level.The secondary shunt is referred to the local power supply of the protected elements to minimize the voltage across individual devices.

This course gives you a complete insight into the modern design of digital systems fundamentals from an eminently practical point of view. The resolution and offset in these two dimensions determine the size of the eyeopening required for reliable detection of the signal.

The receiver sees this reflection as a noise spike that consumes about half of the data eye. In particular. In addition to eliminating the need for most synchronization.

ANNIKA from Flint
Please check my other articles. I'm keen on karate. I do like reading comics shyly .
>